FIG. 8 is a block diagram of a conventional solid-state imaging device disclosed in PTL1. Solid-state imaging device 500 in the figure includes imaging region 510, row selection circuit 520, horizontal scanning circuit 530, timing control circuit 540, ADC group 550, digital-analog converter (DAC) 560 as a ramp signal generator, amplifier circuit 570, signal processing circuit 580, and horizontal transmission line 590. Single slope column-parallel ADC including comparator 551, counter 552, and latch circuit 553 is aligned in multiple columns in ADC group 550.
Comparator 551 compares ramp voltage Vslope that has stepwise ramp waveform output from DAC 560 via ramp signal line 555 with an analog signal output from pixel per row via vertical signal line 554. Counter 552 counts comparison time of comparator 551. By the above operation of comparator 551 and counter 552, ADC group 550 outputs a pixel signal as digital data. The above ADC system is called a single slope column-parallel ADC system.